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low cost, precision jfet input operational amplifiers data sheet ada4 000-1 /a d a4000-2/ada4000-4 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2007C2016 analog devices, inc. all rights reserved. technical support www.analog.com features high slew rate: 20 v/s fast settling time low offset voltage: 1.70 mv maximum bias current: 40 pa maximum 4 v to 18 v operation low voltage noise: 16 nv/ ? hz unity gain stable common-mode voltage includes +v s wide bandwidth: 5 mhz applications reference gain/buffers level shift/driving active filters power line monitoring/control current/voltage sense or monitoring data acquisition sample-and-hold circuits integrators general description the ada4000-1 / ada4000-2 / ada4000-4 are junction field effect transistor (jfet) input operational amplifiers featuring precision, very low bias current, and low power. combining high input impedance, low input bias current, wide bandwidth, fast slew rate, and fast settling time, the ada4000-1 / ada4000- 2 / ada4000-4 are ideal amplifiers for driving analog-to-digital inputs and buffering digital-to-analog converter outputs. the input common-mode voltage includes the positive power supply, which makes the device an excellent choice for high-side signal conditioning. additional applications for the ada4000-1 / ada4000-2 / ada4000-4 include electronic instruments, automated test equipment (ate) amplification, buffering, integrator circuits, instrumentation-quality photodiode amplification, and fast precision filters (including phase-locked loop filters). the devices also include utility functions, such as reference buffering, level shifting, control input/output interface, power supply control, and monitoring functions. pin configurations o ut 1 v? 2 +in 3 v+ 5 ?in 4 ada4000-1 top view (not to scale) 05791-001 fig ure 1. 5-lead tsot (uj-5) nc 1 ?in 2 +in 3 v? 4 nc 8 v+ 7 out 6 nc 5 nc = no connect ada4000-1 top view (not to scale) 05791-002 fig ure 2. 8-lead soic (r-8) out a 1 ?in a 2 +in a 3 ?v 4 +v 8 out b 7 ?in b 6 +in b 5 ada4000-2 top view (not to scale) 05791-027 fig ure 3. 8-lead soic (r-8) out a 1 ?in a 2 +in a 3 ?v 4 +v 8 out b 7 ?in b 6 +in b 5 ada4000-2 top view (not to scale) 05791-028 fig ure 4. 8-lead msop (rm-8) out a 1 ?in a 2 +in a 3 +v 4 out d 14 ?in d 13 +in d 12 ?v 11 +in b 5 +in c 10 ?in b 6 ?in c 9 out b 7 out c 8 ada4000-4 top view (not to scale) 05791-029 figure 5. 14-lead soic (r-14) ada4000-4 1 2 3 4 5 6 7 ?in a +in a +v out b ?in b +in b out a 14 13 12 11 10 9 8 ?in d +in d ?v out c ?in c +in c out d top view (not to scale) 05791-030 figure 6. 14-lead tssop (ru-14)
ada4000-1/ada4000-2/ada4000-4 data sheet rev. b | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? pin configurations ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics ............................................................. 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? power sequencing .........................................................................5 ? esd caution...................................................................................5 ? typical performance characteristics ..............................................6 ? applications information .............................................................. 10 ? output phase reversal and input noise ................................. 10 ? capacitive load drive ............................................................... 10 ? settling time ............................................................................... 11 ? outline dimensions ....................................................................... 12 ? ordering guide .......................................................................... 14 ? revision history 3/16rev. a to rev. b change to figure 12 caption .......................................................... 6 changes to output phase reversal and input noise section and capacitive load drive section .............................................. 10 updated outline dimensions ....................................................... 13 3/09rev. 0 to rev. a changes to input voltage range parameter ................................. 4 changes to common-mode rejection ration parameter .......... 4 updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 14 5/07revision 0: initial version
data sheet ada4000- 1/ada4000 - 2/ada4000 - 4 rev. b | page 3 of 16 specifications electrical character istics v s = 15.0 v, v cm = v s / 2 v, t a = 25c, unless otherwise specified. table 1 . parameter symbol test conditions /comments min typ max unit input characteristics offset voltage v os 0.2 1.70 mv ?40c t a +125c 3.0 mv input bias current i b 5 40 pa ?40c t a +85c 170 pa ?40c t a +125c 4.5 na input offset current i os 2 40 pa ?40c t a +85c 80 pa ?40c t a +125c 500 pa input voltage range ivr ?11 +15 v common - mode rejection ratio cmrr ?11 v v cm +15 v 80 100 db ?40c t a +125c 100 db open - loop gain a vo r l = 2 k?, v o = 10 v 100 110 db offset voltage drift v os /t ?40c t a +125c 2 v/c output characteristics output voltage high v oh r l = 2 k? to ground 13.60 13.90 v ?40c t a +125c 13.40 v output voltage low v ol r l = 2 k? to ground ?13.4 ?13.0 v ?40c t a +125c ?12.80 v short - circuit current i sc 28 ma power supply power supply rejection ratio psrr v s = 4.0 v to 18.0 v 82 92 db supply current/amplifier i sy 1.35 1.65 ma ?40c t a +125c 1.80 ma dynamic performance slew rate sr v i = 10 v, r l = 2 k? 20 v/s gain bandwidth product gbp 5 mhz phase margin m 60 degrees noise performance voltage noise e n p - p 0.1 hz to 10 hz 1 v p -p voltage noise density e n f = 1 khz 16 nv/hz current noise density i n f = 1 khz 0.01 pa/hz input impedance differential mode (r||c) in - diff 10||4 g?||pf common mode (r||c) incm 10 3 ||5.5 g?||pf
ada4000- 1/ada4000 - 2/ada4000 - 4 data sheet rev. b | page 4 of 16 v s = 5 v, v cm = v s / 2 v, t a = 25c, unless otherwise specified. table 2 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os 0.20 1.70 mv ?40c t a +125c 3.0 mv input bias current i b 5 40 pa ?40c t a +85c 170 pa ?40c t a +125c 3 na input offset current i os 2 40 pa ?40c t a +85c 80 pa ?40c t a +125c 500 pa input voltage range ivr ?1.0 +5.0 v common - mode rejection ratio cmrr ?1.0 v v cm +5.0 v 72 80 db ?40c t a +125c 80 db open - loop gain a vo r l = 2 k?, v o = 2.5 v 106 114 db offset voltage drift v os /t ?40c t a +125c 2 v/c output characteristics output voltage high v oh r l = 2 k? to ground 4.0 4.20 v ?40c t a +125c 3.80 v output voltage low v ol r l = 2 k? to ground ?3.45 ?3.20 v ?40c t a +125c ?3.00 v short - circuit current i sc 28 ma power supply supply current/amplifier i sy 1.25 1.65 ma ?40c t a +125c 1.80 ma dynamic performance slew rate sr v i = 10 v, r l = 2 k? 20 v/s gain bandwidth product gbp 5 mhz phase margin m 55 degrees noise performance voltage noise e n p - p 0.1 hz to 10 hz 1 v p -p voltage noise density e n f = 1 khz 16 nv/ hz current noise density i n f = 1 khz 0.01 pa/
data sheet ada4000- 1/ada4000 - 2/ada4000 - 4 rev. b | page 5 of 16 absolute maximum rat ings table 3 . parameter rating supply voltage 18 v input voltage v supply differential input voltage v supply output short - circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximu m operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc unit 5 - lead tsot (uj -5) 172.92 61.76 c/w 8 - lead soic (r - 8) 112.38 61.6 c/w 8 - lead msop (rm - 8) 141.9 43.7 c/w 14- lead soic (r - 14) 88.2 56.3 c/w 14- lead tssop (ru - 14) 114 23.3 c/w power sequencing the operational amplifier supply voltages must be established simultaneously with, or before, any input signals are applied. if this is not possible, the input current must be limited to 10 ma. esd caution
ada4000- 1/ada4000 - 2/ada4000 - 4 data sheet rev. b | page 6 of 16 typical performance characteristics 05791-003 50 45 40 35 30 25 20 15 10 5 0 number of amplifiers ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 offset vo lt age (mv) v s = 15v t a = 25c v cm = 0v figure 7 . input offset voltage distribution, v s = 15 v 05791-004 4 2 0 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 20 number of amplifiers tcv os (v/c) v s = 15v figure 8 . offset voltage drift distribution, v s = 15 v 80 ?20 1k 100m frequency (hz) gain (db) 05791-010 0 20 40 60 180 ?45 phase margin (degrees) 0 45 90 135 10k 100k 1m 10m v s = 15v t a = 25c c l = 35pf 60 figure 9 . open - loop gain and phase margin vs. frequency, v s = 15 v 05791-018 50 45 40 35 30 25 20 15 10 5 0 number of amplifiers ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 offset vo lt age (mv) v s = 5v t a = 25c v cm = 0v figure 10 . input offset voltage distribution, v s = 5 v 05791-019 4 2 0 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 number of amplifiers tcv os (v/c) v s = 5v figure 11 . offset voltage drift distribution, v s = 5 v 80 ?20 1k 100m frequency (hz) gain (db) 05791-020 0 20 40 60 180 ?45 phase margin (degrees) 0 45 90 135 10k 100k 1m 10m v s = 5v t a = 25c c l = 35pf 55 figure 12 . open - loop gain and phase margin vs. frequency , v s = 5 v
data sheet ada4000- 1/ada4000 - 2/ada4000 - 4 rev. b | page 7 of 16 120 20 100 10m frequency (hz) cmrr (db) 05791-013 40 60 80 100 1k 10k 100k 1m v s = 15v t a = 25c figure 13 . common - mode rejection ratio vs. frequency, v s = 15 v 15 ?15 time (1 s/div) voltage (v) 05791-015 ?5 10 0 5 ?10 v s = 15v a v = +1 r l = 2k ? t a = 25c figure 14 . large signal transient response, v s = 15 v time (2s/div) voltage (20mv/div) v s = 15v c l = 300pf a v = +1 t a = 25c 05791-016 figure 15 . small signal transient response, v s = 15 v 100 20 1k 10m frequency (hz) cmrr (db) 05791-021 60 10k 100k 1m 80 40 v s = 5v t a = 25c figure 16 . common - mode rejection ratio vs. frequency, v s = 5 v time (1 s/div) voltage (v) 05791-023 4 3 2 1 0 ?1 ?2 ?3 ?4 v s = 5v a v = ?1 r l = 2k ? t a = 25c figure 17 . large signal transient response, v s = 5 v time (2s/div) voltage (20mv/div) 05791-024 v s = 5v c l = 300pf a v = +1 t a = 25c figure 18 . small signal transient response, v s = 5 v
ada4000- 1/ada4000 - 2/ada4000 - 4 data sheet rev. b | page 8 of 16 3.5 1.0 5 15 supply voltage (v) input bias current (pa) 05791-006 3.0 2.5 2.0 1.5 6 7 8 9 10 1 1 12 13 14 t a = 25c figure 19 . input bias current vs. supply voltage 10000 ?40 temperature ( c ) input bias current (pa) 05791-005 1 0.1 10 100 1000 ?25 ?10 5 20 35 50 65 80 95 110 125 v s = 15v v s = 5v figure 20 . input bias current vs. temperature 1.44 1.20 ?40 125 temperature (c) supply current (ma) 05791-012 1.40 1.36 1.32 1.28 1.24 ?25 ?10 5 20 35 50 65 80 95 110 v s = 5v v s = 15v figure 21 . supply current vs. temperature 1.40 1.35 1.30 1.25 1.20 1.15 1.10 supply current (ma) 4 5 6 7 8 9 10 11 12 13 14 15 supply voltage (v) 05791-008 t a = 25c no load figure 22 . supply current vs. supply voltage 16 0 0 25.0 load current (ma) output voltage (v) 05791-009 14 12 10 8 6 4 2 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 v s = 15v v s = 5v |v ol | v oh |v ol | v oh figure 23 . output voltage vs. load current 120 ?20 100 10m frequency (hz) psrr (db) 05791-014 20 80 1k 10k 100k 1m 100 40 60 0 v s = 5v, 15v psrr? psrr+ figure 24 . psrr vs. frequency
data sheet ada4000- 1/ada4000 - 2/ada4000 - 4 rev. b | page 9 of 16 10 100 1k 100 1 1 10k frequenc y ( hz ) vo lt age noise densit y (nv/ hz) 05791-026 10 v s = 5 v , 15v t a = 25c figure 25 . voltage noise density vs. frequency 120 0 1k 100m frequency (hz) z out ( ? ) 05791-017 60 80 10k 100k 1m 10m 100 20 40 v s = 15v t a = 25c a v = +100 a v = +10 a v = +1 figure 26 . output impedance vs. frequency 60 0 0 600 400 200 load capacitance (pf) overshoot (%) 05791-022 800 1000 50 40 30 20 10 v in = 100mv p-p v s = 5v, 15v r l = 0 a v = +1 +overshoot ?overshoot figure 27 . overshoot vs. load capacitance 0.6 ?0.6 ?5 time (seconds) v p-p (v) 05791-025 5 0.4 0.2 0 ?0.2 ?0.4 ?4 ?3 ?2 ?1 0 1 2 3 4 v s = 5v, 15v figure 28 . 0.1 hz to 10 hz input voltage noise 50 ?30 100 1k 100m frequency (hz) closed-loop gain (db) 05791-0 1 1 ?10 0 30 10k 100k 1m 10m 40 10 20 ?20 a v = +100 a v = +10 a v = +1 v s = 5v, 15v figure 29 . closed - loop gain vs. frequency
ada4000-1/ada4000-2/ada4000-4 data sheet rev. b | page 10 of 16 applications information output phase reversal and input noise phase reversal is a change of polarity in the transfer function of the amplifier. this can occur when the voltage applied at the input of the amplifier exceeds the maximum common-mode voltage. phase reversal happens when the device is configured in the gain of 1. most jfet amplifiers invert the phase of the input signal if the input exceeds the common-mode input. phase reversal is a temporary behavior of the ada4000-1 / ada4000-2 / ada4000-4 family. each device returns to normal operation by bringing back the common-mode voltage. the cause of this effect is saturation of the input stage, which leads to the forward-biasing of a drain- gate diode. in noninverting applications, a simple fix for this is to insert a series resistor between the input signal and the non- inverting terminal of the amplifier. the value of the resistor depends on the application, because adding a resistor adds to the total input noise of the amplifier. the total noise density of the circuit is ?? s s nn ntotal ktrriee 4 2 2 ??? where: e n is the input voltage noise density of the device. i n is the input current noise density of the device. r s is the source resistance at the noninverting terminal. k is boltzmanns constant (1.38 10 ?23 j/k). t is the ambient temperature in kelvin (t = 273 + c). in general, it is good practice to limit the input current to less than 5 ma to avoid driving a great deal of current into the amplifier inputs. capacitive load drive the ada4000-1 / ada4000-2 / ada4000-4 are stable at all gains in both inverting and noninverting configurations. the devices are capable of driving up to 1000 pf of capacitive loads without oscillations in unity gain configurations. however, as with most amplifiers, driving larger capacitive loads in a unity gain configuration can cause excessive overshoot and ringing. a simple solution to this problem is to use a snubber network (see figure 30). ada4000-1 v+ v? +15 v ?15v r s c s c l 500pf r l 10k? 0 snubber network 400mv p-p 05791-031 0 v1 3 2 1 u1 figure 30. snubber network configuration the advantage of this compensation method is that the swing at the output is not reduced because r s is out of the feedback network, and the gain accuracy does not change. depending on the capacitive loading of the circuit, the values of r s and c s change, and the optimum value can be determined empirically. in figure 31, the oscilloscope image shows the output of the ada4000-1 / ada4000-2 / ada4000-4 family in response to a 400 mv pulse. the circuit is configured in the unity gain configuration with 500 pf in parallel with 10 k of load capacitive. 05791-032 time (1s/div) voltage (200mv/div) input signal output signal figure 31. capacitive load drive without snubber network when the snubber circuit is used, the overshoot is reduced from 30% to 6% with the same load capacitance. ringing is virtually eliminated, as shown in figure 32. in this circuit, r s is 41 and c s is 10 nf. 05791-033 time (1s/div) voltage (200mv/div) input signal output signal figure 32. capacitive load with snubber network
data sheet ada4000-1/ada4000-2/ada4000-4 rev. b | page 11 of 16 settling time settling time is the amount of time it takes the amplifier output to reach and remain within a percentage of the final value. this is an important parameter in data acquisition systems. because most bipolar dac converters have current output, an external operational amplifier is required to convert the current to voltage. therefore, the amplifier settling time plays a role in the total settling time of the output signal. a good approximation for the total settling time is 2 2 )()( amptdacttotalt s s s ? ? the ada4000-1 / ada4000-2 / ada4000-4 settle to within 0.1% of their final value in less than 1.2 s. the settling time has been tested by using the configuration circuit in figure 34. the input signal is a 10 v pulse and the output is the error signal for the settling time shown in figure 33. 05791-035 200ns/div 200mv/div 5v/div figure 33. settling time measurement using the false summing node method ada4000-1 v+ v? +15 v ?15v 10v p-p 05791-034 3 2 1 10k ? 10k ? 10k? ad828 v+ v? +15v ?15v 20k ? v out 1k? 8 4 10k ? v1 0 figure 34. settling time test circuit
ada4000- 1/ada4000 - 2/ada4000 - 4 data sheet rev. b | page 12 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-a a 012407- a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) sea ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarit y 0.10 figure 35 . 8 - lead standard small outline package [soic_ n] narrow body (r - 8) dimensions shown in millimeters and (inches) 100708-a * compliant to jedec standards mo-193-ab with the exception of package height and thickness. 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max * 1.00 max * 0.90 max 0.70 min 2.90 bsc 5 4 1 2 3 se a ting plane figure 36 . 5 - lead thin small outline transistor package [tsot] (uj - 5) dimensions shown in millimeters
data sheet ada4000- 1/ada4000 - 2/ada4000 - 4 rev. b | page 13 of 16 compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 37 . 8 - lead mini small outl ine package [msop] (rm - 8) dimensions shown in millimeters compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 sea ting plane figure 38 . 14 - lead standard small outline package [tssop] (ru - 14) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc se a ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45 figure 39 . 14 - lead standard small outline package [soic_n] (r - 14) dimensions shown in millimeters
ada4000-1/ada4000-2/ada4000-4 data sheet rev. b | page 14 of 16 ordering guide model 1 temperature range package description package option branding ada4000 -1 ar 40c to +125c 8- lead soicn r-8 ada4000 -1 ar -r7 40c to +125c 8- lead soicn r-8 ada4000 -1 ar -rl 40c to +125c 8- lead soicn r-8 ada4000 -1 auj -r2 40c to +125c 5- lead tsot uj -5 a14 ada4000 -1 auj -r7 40c to +125c 5- lead tsot uj -5 a14 ada4000 -1 auj -rl 40c to +125c 5- lead tsot uj -5 a14 ada4000 -2 ar 40c to +125c 8- lead soicn r-8 ada4000 -2 ar -r7 40c to +125c 8- lead soicn r-8 ada4000 -2 ar -rl 40c to +125c 8- lead soicn r-8 ada4000 - 2 arm 40c to +125c 8 - lead msop rm - 8 a1h ada4000 -2 arm - rl 40c to +125c 8- lead msop rm -8 a1h ada4000 - 4 ar 40c to +125c 14 - lead soicn r - 14 ada4000 - 4 ar - r7 40c to +125c 14 - lead soicn r - 14 ada4000 -4 ar -rl 40c to +125c 14- lead soicn r- 14 ada4000 -4 aru 40c to +125c 14- lead tssop ru -14 ada4000 -4 aru - rl 40c to +125c 14- lead tssop ru -14 1 rohs compliant part.
data sheet ada4000- 1/ada4000 - 2/ada4000 - 4 rev. b | page 15 of 16 notes
ada4000- 1/ada4000 - 2/ada4000 - 4 data sheet rev. b | page 16 of 16 notes ? 2007 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05791 - 0 - 3/16(b)

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